This disclosure relates, in general, to image sensors and, in particular, to readout circuits for such sensors.
Image sensors find applications in a wide variety of fields, including machine vision, robotics, guidance and navigation, automotive applications, and consumer products. In many smart image sensors, it is desirable to integrate on-chip circuitry to control the image sensor and to perform signal and image processing on the output image. Unfortunately charge-coupled device (CCD), which have been one of the dominant technologies used for image sensors, do not easily lend themselves to large scale signal processing and are not easily integrated with CMOS circuits. Moreover, a CCD is read out by sequentially transferring the signal charge through the semiconductor, and the readout rate is limited by the need for nearly perfect charge transfer.
Active pixel sensors (APS), which have one or more active transistors within the pixel unit cell, can be made compatible with CMOS technologies and promise higher readout rates compared to passive pixel sensors. Active pixel sensors are often arranged as arrays of elements, which can be read out, for example, a column at a time. As it is read out, each column is driven and buffered for sensing by a readout circuit.
The analog signals that are read out from the sensor array typically are converted to digital signals to facilitate subsequent processing of the image. During analog-to-digital conversion, a reference voltage can be used to generate digital representations of the analog input signals. Signal resolution often is maximized when the expected range of the analog input signal matches the reference voltage level. However, in some situations, the output of the CMOS image sensor has a relatively low voltage level due to a low light condition or operation at a high frame rate. Thus, in such situations, it may be necessary or desirable to amplify the output signals from the CMOS image sensor to provide a stronger analog input signal to the analog-to-digital converter (ADC).
In some imagers, a single readout stage is used to an entire array of pixels. Recently, there has been heightened interest in parallel column architectures to increase the overall speed and/or accuracy of the output stage. However, in the past, size and power constraints have limited the extent to which such architectures could be implemented for a CMOS imager.